Itanium® Architecture for Programmers


Rumors about future Itanium processors

We do not aspire to predict the future, but we are as curious as anyone else about what may lie ahead. The material in the tables below comes either from vendor web sites or from other places on the Internet. Treat everything as just possibilities and nothing as promises!

Road map information from Intel web sites and sources
2003-2006 2006 2008? 2008? 2011?
Code names

MP (high-end)

DP (low-end)






DP Montvale


Pin-compatibility with Itanium 2     yes yes yes ?
Process 130 nm 90 nm 90 nm
L3 cache (max per core) 9 MiB 12 MiB
Front-side bus speed (max) 667 MHz 533 MHz
Processor speed (max) 1.7 GHz 1.6 GHz
Power (max per chip) 130 W 104 W
Core multiplicity (max) single dual dual? quad
Speculation from other web sites or trade press
2007 2008 later later
Code name


(formerly Tanglewood)

(technology from Alpha)

(on-chip memory controller)
Dimona (budget version) Poulson
Pin-compatibility with Itanium 2     yes
Process 90 nm 65 nm
Die size 300 sq mm
Millions of transistors
L3 cache (max per core) 6 MiB
Front-side bus speed
Processor speed(s) 2.0-2.2 GHz 2.5 GHz
Core multiplicity (max) dual 4 cores


Other 64-bit processors

While this page is part of a web site in support of our book about Itanium architecture, we are interested in other architectures also. The following processors have been mentioned recently in articles in the trade press.


Advanced Micro Devices extended the industry-standard x86 CISC architecture from a 32-bit datapath with only 8 integer registers to the 64-bit AMD64 instruction set architecture with 16 integer registers. Beginning with Opteron processors intended for the server market and continuing with Athlon64 processors for desktop systems, this transition extended to the Turion and finally in 2006 to the Sempron processors for mobile systems.

2006: chips with 65 nm feature sizes

2007: quad-core desktop processors; 2 MiB L3 cache shared among cores

2008: chips with 45 nm feature sizes

2010: chips with 32 nm feature sizes

At some point, the Hypertransport interconnect will be enhanced to allow intermixing non-AMD coprocessors with AMD cores on the same main chip.


Because of prior legal settlements, Intel and AMD have certain cross-licensing agreements in place. Intel's EM64T (Extended Memory 64 Technology), with instruction extensions essentially conforming to the AMD64 architecture, first reached the market as 64-bit Xeon processors in 2004. As of 2006, some Intel x86 processors still have 32-bit integer datapaths. Intel's processors do not yet have on-chip memory control as found in AMD's processors, but typically do have much larger on-chip cache structures.

2006: most chips to have 65 nm feature sizes; dual-core chips available in most product lines

2008: chips with 45 nm feature sizes; four cores (as two pairs?)

2008: some 50 new instructions (SSE4 and “application targeted accelerators”)

2010: chips with 32 nm feature sizes

2016+: possible chips based on indium antimonide (III-V semiconductor)

VIA Technologies?

VIA Technologies makes x86 chips with very low power dissipation (3-20 W) for mobile devices and embedded applications.

2006: an "Isaiah" 64-bit processor core (engineering code name 'CN') was announced as under development in 2004, but we do not know whether it may emerge as AMD64/EM64T compatible.


For several years, IBM has based many of server systems on its own POWER (Performance Optimization with Enhanced RISC) family of processors, currently dual-core chips called Power5+ with 90 nm feature sizes, which can be packaged into quad-core modules for a single socket.

2007: Power6 with 65 nm feature sizes and “squeezed” silicon to make it faster; dual-threaded dual-core with 4 MiB L2 cache per core; up to 32 MiB off-chip L3 cache; 700 million transistors; 341 square millimeters; instructions for binary coded decimal arithmetic (BCD); AltiVec (XVM) multimedia instructions from the PowerPC; 4-5 GHz processor speed; bus speed 300 GBps.

2010?: Power7

IBM, Apple, and Motorola (later spun off as Freescale) collaborated on PowerPC processors, which were derivatives of IBM's Power architecture and used in Apple Macintosh products until 2006. Motorola and Freescale produced only 32-bit PowerPC processors; IBM furnished some 32-bit processors as well as the 64-bit "G5" to Apple.

IBM has codeveloped the 4 GHz Cell Broadband Engine processor with Toshiba and Sony for use in gaming stations and other multimedia appliances or servers; it has a 64-bit PowerPC processing core supplemented by eight special-purpose engines for handling graphics or numeric calculations. A second generation will run at 6 GHz.

P.A. Semi

A new company, P.A. Semi plans a line of PWRficient processors based on the POWER architecture.

2007: single- and multi-core 2 GHz system-on-chip low power dissipation (25 W) products based on a ground-up PA6T core design; 115 square millimeters.

64-bit Freescale?

Freescale Semiconductor, a spinoff from Motorola, produces 32-bit processors conforming to the PowerPC architecture, but not yet 64-bit processors. (In September 2006, Freescale noted that it might be taken private in a buy-out of its publicly traded stock.)

Sun Microsystems

Like the MIPS architecture (see below), the Sparc architecture began as a 32-bit RISC design, but was later extended to 64-bit registers and datapath. An independent administrative body called SPARC International manages the architectural specification of the SPARC V9 instruction set.

Several current variants of the architecture are used in Sun products: single-core UltraSparc IIi, III, and IIIi; dual-core IV+, quad-threaded 4-, 6-, or 8-core UltraSparc T1, and SPARC64-V.

2007: UltraSparc T2 (formerly code named Niagara II), 65 nm process, able to execute as many as 64 threads (8 threads per core); separate floating-point pipeline for each core, in contrast to one unit shared by all cores in the UltraSparc T1

2008: Rock code name family of higher-end multi-core chips, 65 nm process

later: dual processor and higher speed versions of UltraSparc T2

later: code name Niagara III, more cores and threads, 45 nm process

later: follow-on versions of Rock, 45 nm process


Current PRIMEPOWER servers, which are also sold by Sun, contain Fujitsu's SPARC64 V implementation of the SPARC V9 instruction set on a 90 nm process.

2007: Olympus code name family of SPARC64 VI dual-core dual-thread processors, 65 nm process; 6 MiB shared cache

later: Jupiter code name family of SPARC64 VI+ quad-core dual-thread processors, 65 nm process; 6 MiB shared cache

Simply RISC

Under the open-design policy of Sun, Simply RISC developed S1 Core as a single-core processor based on the UltraSparc T1 and capable of running Unix or Linux for embedded applications.


Founded by Seymour Cray, merged with SGI in 1996, and finally purchased in 2000 by Tera Computer, another supercomputer company which then renamed itself Cray, Cray now makes some supercomputers using a specialized 64-bit CPU design with quad-threaded processors that had been designed by Tera Computer and that support an instruction set architecture including vector as well as ordinary scalar arithmetic. Cray makes other supercomputers using Opteron processors from AMD.


Previously owned by Silicon Graphics, but now independent again, MIPS Technologies develops and licenses 64- and 32-bit architectures in the form of small, low-power "cores" that companies can incorporate into SoC (system on a chip) products. The 64-bit architecture is an extension of an earlier 32-bit RISC instruction set architecture.

Silicon Graphics phased out MIPS-based systems and its own IRIX variant of the Unix operating system in 2006. Hewlett-Packard has begun changing its NonStop servers from high-performance MIPS chips to Itanium 2 chips, and will phase out the former.

64-bit ARM?

The British chip designer ARM presently offers only a 32-bit architecture with a large share of the worldwide market for embedded processors. The latest ARM10 architecture has 64-bit instruction and data buses, but not 64-bit registers.

Abandoned 64-bit processors

Technological trends, development costs, and sequences of consolidations among corporations in the industry have led to a decrease in the number of truly different 64-bit architectures. We list here the final offering in former product lines.

Alpha (Digital Equipment Corporation, Compaq, Hewlett-Packard)

Implementing a de novo 64-bit RISC architecture, Alpha chips were introduced in 1992 for use in scientific workstations and servers. The final EV7 (a.k.a 21364) Alpha chip was released by Hewlett-Packard in 2003 for use in server products that were then discontinued in 2006.

PA-RISC (Hewlett-Packard)

Implementing a RISC architecture first designed in 1986 for 32 bits and extended to 64 bits a decade later, PA-RISC chips have been used in scientific workstations and servers. The final PA-8900 chip was released by Hewlett-Packard in 2006 for use in one final generation of RISC-based servers that will eventually be discontinued, since replacements based on Itanium 2 processors are already available.

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