| Computer Science 430 | Assignment 06 | Winter 2010–11 |
Keep up with the indicated pace of reading in each chapter for class.
Submit your solutions to the following problems, most of which are specific exercises from the end of chapter 5 of the book by Patterson and Hennessy, by 1:00 PM, Thursday, 03 March 2011. You may hand in your work at Science Hall 131, if it is open, or at the faculty mailboxes in Briggs.
| 1. | The first Itanium processor had a 64-bit datapath, but supported only 44-bit physical addresses into the memory hierarchy with three levels of cache. Level 2 cache operated as a combined instruction and data repository. This cache had 96 x 210 bytes of usable payload capacity organized with 6-way associativity and a 64-byte block size. Work out all of the numeric bit-level parameters in the manner shown in Figure 5.17 of the 4th edition of the text by Patterson and Hennessy. | |
| 2. | Exercise 5.3.2b | |
| 3. | Exercise 5.8.1b | |
| 4. | Compare the hit ratios of the cache designs described in Exercise 5.3.2b and 5.8.1b. Compare their costs assuming that the cost of a cache is proportional to its overall size, i.e. the payload blocks plus the overhead fields (V, tag, etc.). | |
| 5. | Exercise 5.10.1a | |
| 6. | Exercise 5.10.4b | |
| 7. | Exercise 5.11.1a |
For work of this sort, some indication of method (not just final result) is appropriate.
Note that the final deadline for all written work in this course will be 1:00 PM, Thursday, 10 March 2011.