Computer Science 440 Computer Architecture Spring 2009–10

Equivalent web page:
Catalog description: Viewable at
James S. Evans
Science Hall 131
Extension 6571
Home: 734-6304 (not after 10:00 PM, please)
Office hours: You may either make a specific appointment, or just stop by the office any time that the door is open (that will be most of the time).
Class meetings: 8:30–9:40 M W F, Briggs Hall 419
Text: Itanium Architecture for Programmers: Understanding 64-bit Processors and EPIC Principles by James S. Evans (Lawrence University) and Gregory L. Trimper (viika), published by Prentice Hall Professional in the Hewlett-Packard Professional Books series, ISBN 0-13-101372-6 (2003).
Supporting web site:; mirror site
Coverage: The course will include most of the material in the text. Assignments may require that you combine knowledge and skills gained from the text, class presentations, and other reference sources. Through an individual project, you will compare another computer architecture to the Itanium architecture.
Host Itanium computer access: The generosity of technical staff of Hewlett-Packard Company has brought us two Itanium-based workstation-class systems that are located in the Molecular Informatics Laboratory (Science Hall 130) and accessible over the internal campus network.
  Model zx2000 zx6000
  name mckinley.acadsvr stone.acadsvr
  Specs one 900MHz Itanium 2   
two 900MHz Itanium 2
/6GiB/2x36GB RAID 0
  System software Red Hat AWS 6.1 HP-UX 11i version 1.6
  IP number
  Access modes ssh, sftp telnet, ftp
Each person will have an individual account on one or more of these workstations. See Appendix B.3 in the text and the updated information on the supporting web site for information about client access software. Some of these hosts may also accept access using the X Window System.
Simulated Itanium environments:  One possibility is to configure the Ski simulator from Hewlett-Packard in the open-source Native User Environment on a 32-bit Linux system. Note that Simics from Virtutech (mentioned in Appendix B) no longer supports Itanium as a target system.
Host AMD64 computer access: Most computers based on AMD64 or Intel 64 processors can run a 64-bit Windows operating system or Linux, for comparison with a different 64-bit architecture.
Rationale for this course: Some insight into the nature of assembly language programming can be gained from Assemblers and Loaders by D. W. Barron. In the preface to the first edition (1968), he wrote that the study of assemblers and loaders “makes an excellent introduction to advanced programming for the student of computer science, or the professional programmer who is interested in what goes on behind the scenes.” In the second edition (1971), he felt able to write that recent developments “herald the end of assembly language programming as we have known it.” In the third edition (1978), however, he remarked that “the explosive development of mini- and micro-computer hardware has given assembly language programming a new lease on life.”
Perhaps Barron hit closest to the mark the first time. An exposure to assembly language programming can provide an emphasis on disciplined analysis, a clearer sense of structure in software systems, and a deeper appreciation for similarities and differences among types of computer hardware.
The Itanium architecture, based on a decade of research at HP Labs combined with the manufacturing experience of Intel Corporation, makes a good vehicle with which to acquire this experience, since it represents a distinctive 64-bit design, yet shares some concepts and compatibilities with such progenitors as the 64-bit HP PA-RISC processors and the internally complex 32-bit Intel processors.
With experience from this course, and/or from the companion Hardware Organization course (CMSC 430), you will be better able to comprehend the technical basis for what you may read in the media about, for instance, the initial questions about any superiority of the Pentium 4 over the Pentium III.
Assessments: Frequent problem assignments, an individual project, two in-class exams, and the final examination will form the basis for evaluation.
     Assignments 45%
Individual project 10%
Hour exams 20%
Final exam 25%
The cumulative distribution of grades for this course in previous years from this instructor has been as follows: A, 32%; B, 35%; C, 21%; D, 7%; F, 5%. These percentages are merely history, however, and in no way represent quotas or promises for this year.
Assignments: There will be many assignments, coming along after every two or three class meetings.
Assignments are due at 1:00 PM on the stated day. Late work is never fun to evaluate. Each student will begin the term with a “contingency” account containing 10 “contingency points.” When an assignment is late, this account reduces at the rate of 2 points per calendar day (or fraction thereof). If an assignment can be completed nicely and handed in earlier than 5:00 PM preceding the stated due date, then additional contingency points can be accrued at a rate of 1 per calendar day. The contingency account uses signed integer arithmetic. At the end of the term, the balance may be used to resolve ultimate grading decisions, but there is no predetermined relationship of contingency points to the standard grading scale.
Programs must be demonstrated to function, of course, but efficiency, adequacy of design, clarity of program flow, and thoroughness of commenting are also important. Highest rewards will be reserved for that work which makes the reader confident about its reliability and the ease with which another competent programmer could extend or modify the program entity. Mere cleverness may be noticed but not necessarily praised.
Individual project: The principal illustration in class will be the Itanium architecture. Class members will also explore other contemporary or recent architectures independently as individual projects. Each person should make a different choice, to the extent possible, although small groups might collaborate provided that more ambitious goals are set.
Note that there are substantial built-in penalties against procrastination on this project, since the tentative schedule (see below) defines several interim milestones to be met.
Honor code: Each piece of work that you submit in this course should bear the Lawrence University honor pledge, your signature, and the date of completion on the final page.
Please seek help from others whenever you can learn effectively in the process, but always acknowledge the source, nature, and extent of assistance or collaboration. The final product should be distinctively your own.
Assistance: CMSC 440 is an advanced-level opportunity intended for mature students who can seek out assistance well in advance of the fabled “point of desperation.” Please bring any ambiguities in the assigned work or any lack of clarity in class presentations to the instructor’s attention immediately.
Tentative schedule: Keeping up with the brisk pace of this course is essential. If possible, we will try to leave time for additional special topics or the use of class meeting times for optional presentations of individual projects. There are 28 class periods in the official spring term this year. If two periods are taken up by hour exams, then there are 26 actual times for group discussion. The material can be divided into three broad segments: fundamental topics (Chapters 1 through 5), more realistic programming situations (Chapters 6 through 9), and further explorations (Chapters 10 through 13).
Most chapters can probably be discussed in two class periods. If we get pressed for time, Chapters 8 and 12 could be expendable.
Week Day Date Class Activity Assignment or Project
1 Mon  29 Mar  Chapter 1
Wed  31 Mar  Chapters 1 and 2
Fri  02 Apr  Chapter 2
Sat  03 Apr  Assignment 1 due at 1:00 PM
2 Mon  05 Apr  Chapter 3
Tue  06 Apr  Assignment 2 due at 1:00 PM
Wed  07 Apr  Chapter 3
Fri  09 Apr  Chapters 3 and 4 Declaration of intent, i.e., choice of architecture (5% of project grade)
3 Sun  11 Apr  Assignment 3 due at 1:00 PM
Mon  12 Apr Chapter 4
Wed  14 Apr Chapter 4
Fri  16 Apr  Chapter 5
Sat  17 Apr  Assignment 4 due at 1:00 PM
4 Mon  19 Apr  Chapter 5 List of printed and Web sources found (10% of project grade)
Wed  21 Apr  Hour exam
Fri  23 Apr  Chapter 6
Sat  24 Apr  Assignment 5 due at 1:00 PM
5 Mon  26 Apr  Chapter 6
Wed  28 Apr  Chapters 6 and 7
Fri  30 Apr  Chapter 7 Outline and proposed length of paper (15% of project grade)
6 Sun  02 May  Assignment 6 due at 1:00 PM
Mon  03 May  Chapter 7
Wed  05 May  Chapter 8
Fri  07 May  no class (reading period)
7 Mon  10 May  Chapter 8 Assignment 7 due at 1:00 PM
Wed  12 May  Hour exam
Fri  14 May  Chapter 9
8 Sun  16 May  Partial or rough version of paper (20% of project grade)
Mon  17 May  Chapter 9
Tue  18 May  Assignment 8 due at 1:00 PM
Wed  19 May  Chapters 9 and 10
Fri  21 May  Chapter 10
9 Sun  23 May  Assignment 9 due at 1:00 PM
Mon  24 May  Chapters 10 and 11
Wed  26 May  Chapter 11
Thu  27 May  Assignment 10 due at 1:00 PM
Fri  28 May  Chapter 12
10 Mon  31 May  no class (Memorial Day)
Tue  01 Jun  Assignment 11 due at 1:00 PM
Wed  02 Jun  Chapter 13 and/or optional presentations Final version of paper (50% of project grade)
Fri  04 Jun  Optional presentations and wrap-up Assignment 12 due at 1:00 PM
Sat  05 Jun  Final deadline for all written work is 1:00 PM
11 Wed  09 Jun  Final examination at 8:30 AM
More references: Some of these additional references are available in the Lawrence University library. Others are available in the instructor’s office, where you can also find many of the other titles that are listed on the supporting web page for the text. Note that some of the items are rather dated, but may still be useful for background.
RISC  Alpha architecture Alpha Architecture by Richard L. Sites and Dirk Meyer, Stanford, CA: University Video Communications, 1992 [QA76.9.A73 S5 (videocassette)]
The Design of the Alpha 21064 CPU Chip by James J. Montanaro, Stanford, CA: University Video Communications, 1992 [QA76.9.A73 M6 (videocassette)]
“Digital’s Alpha Chip Project” [series of articles], Communications of the ACM 36 (2), 30-83, 1993 [library periodical]
PA-RISC architecture PA-RISC Design Issues by Michael J. Mahon, Stanford, CA: University Video Communications, 1992 [QA76.5 .M1882 (videocassette)]
“Four-Way SuperScalar PA-RISC Processors” by Anne P. Scott, Kevin P. Burkhart, Ashok Kumar, Richard M. Blumberg, and Gregory L. Ranson, Hewlett-Packard Journal 48 (4), 8-15, 1997.
POWER and PowerPC architecture “The Making of the PowerPC” [series of articles], Communications of the ACM 37 (6), 22-69, 1994 [library periodical]
POWER2+ Processor by David J. Shippy, Stanford, CA: University Video Communications, 1994 [QA76.88 .P68 (videocassette)]
There is considerable information available on newer versions of the POWER architecture (consult instructor if you cannot find it)
CISC  IA-32 architecture  An Overview of Intel’s Pentium Processor by John Crawford, Don Alpert, and Beatrice Fu, Stanford, CA: University Video Communications, 1993 [QA76.8.P46 C73 (videocassette)]
AMD64 architecture  Also known as Intel 64 (formerly EMT64); considerable information is available on the AMD and Intel corporate Web sites (consult instructor if you cannot find it; a web page under development is not ready for public posting)
Embedded  systems StrongArm architecture  Although StrongArm chips are very widely used, there are also products by Freescale (spin-off from Motorola), Intel, Texas Instruments, VIA Technologies, and others.